TSMC Unveils N4X Node: Extreme High-Performance at High Voltages

TSMC this week announced a new manufacturing process designed specifically for high performance computing (HPC) products. N4X promises to combine the transistor density and design rules of TSMC’s N5 family nodes with the ability to drive chips at extra high voltages for higher frequencies, which will be particularly useful for server CPUs and SoCs. Interestingly, TSMC’s N4X can potentially enable higher frequencies than even the company’s next-gen N3 process.

One of the problems caused by the downsizing of transistors is the downsizing of their contacts, which means higher contact resistance and consequent problems with power delivery. Various manufacturers use different ways to approach the problem of contact resistance: Intel uses cobalt contacts instead of tungsten contacts, while other manufacturers chose to form contacts using selective tungsten deposition technology. While these methods work perfectly for almost all types of chips, there are still ways to further improve power delivery for High Performance Computing (HPC) designs, which are relatively immodest about the total power / voltage used. . This is exactly what TSMC did to your N4X node. But before we go into the details about the new manufacturing process, let’s see what advantages TSMC promises with it.

TSMC claims that its N4X node can enable clocks up to 15% higher compared to a similar circuit made with N5, as well as up to 4% higher frequency compared to an IC produced using its N4P node while operating at 1.2V. . Also, and seemingly more importantly, N4X can reach drive voltages beyond 1.2V for even higher clocks. To put the numbers in context: Apple’s M1 family SoCs made on N5 run at 3.20 GHz, but if these SoCs were produced using N4X then using TSMC math they could theoretically be pushed to around 3, 70 GHz or an even higher frequency at voltages higher than 1.2V.

TSMC does not compare the transistor density of the N4X with other members of its N5 family, but typically processors and SoCs for HPC applications are not designed with high-density libraries. Power wise, drive voltages over 1.2V will naturally increase power consumption compared to chips produced with other N5 class nodes, but since the node is designed for HPC / data center applications , its focus is to provide the highest possible performance with energy a secondary concern. In fact, total power consumption has increased in HPC-class GPUs and similar parts over the last few generations, and there is no sign of this stopping for the next two generations of products, thanks in part to N4X.

“HPC is now TSMC’s fastest growing business segment and we are proud to introduce N4X, the first in the ‘X’ lineage of our extreme performance semiconductor technologies,” said Dr. Kevin Zhang, Senior Vice President of Development TSMC commercial. “The demands of the HPC segment are relentless, and TSMC has not only adapted our ‘X’ semiconductor technologies to unleash maximum performance, but also combined them with our advanced 3DFabric packaging technologies to deliver the best HPC platform.”

Announced PPA Improvements of New Process Technologies
Data Announced During Conference Calls, Events, Press Conferences, And Press Releases
TSMC
N5
vs
N7
N5P
vs
N5
N5HPC
vs
N5
N4
vs
N5
N4P
vs
N5
N4P
vs
N4
N4X
vs
N5
N4X
vs
N4P
N3
vs
N5
Energy-30%-10%?lower-22%??-25-30%
Performance+ 15%+ 5%+ 7%higher+ 11%+ 6%+ 15%
or
plus
+ 4%
or more
+ 10-15%
Logical area

% Reduction

(Density)

0.55x

-Four. Five%

(1.8x)

0.94 times

-6%

1.06x

0.94 times

-6%

1.06x

?

?

0.58x

-42%

(1.7 times)

Volume
Manufacturing
Q2 20202021S2 202220222023H2 2022H1
2024?
H1 2024?H2 2022

In an attempt to increase performance and make drive voltages greater than 1.2 V possible, TSMC had to evolve the entire process stack.

  • First, it redesigned its FinFET transistors and optimized them for both high clocks and high drive currents, which likely means reducing resistance and parasitic capacitance and increasing current flow through the channel. We don’t know if it had to increase the door-to-door pitch spacing and at this point TSMC doesn’t say what exactly it did and how it affected the transistor density.
  • Second, it introduced new high-density metal-insulator-metal (MiM) capacitors for stable power delivery under extreme loads.
  • Third, he redesigned the end-of-line metal stack to deliver more power to the transistors. Again, we don’t know how this affected the density of the transistor and ultimately the size of the dies.

To a large extent, Intel made similar improvements to its 10nm Enhanced SuperFin process technology (now called Intel 7), which is not surprising, as these are natural methods of increasing frequency potential.

What is spectacular is how significantly TSMC managed to increase the clock speed potential of its N5 technology over time. A 15% increase brings N4X closer to its next-generation N3 manufacturing technology. Meanwhile, with drive voltages above 1.2V, this node will allow higher clocks than N3, making it particularly good for data center CPUs.

TSMC says it expects the first N4X designs to go into risky production by the first half of 2023, which is a very vague description of time, as it can mean very late 2022 or early 2023. In any case, generally It takes a year for a chip to go from risk production to high-volume production iteration, so it is reasonable to expect the first N4X designs to hit the market in early 2024. This is perhaps a weakness of N4X, as by when your N3 will go full throttle and while N4X promises to have an advantage in terms of clocks, N3 will have a huge advantage in terms of transistor density.

Fountain: TSMC

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