Intel Executive Posts Thunderbolt 5 Photo then Deletes It: 80 Gbps and PAM-3

An executive visiting various research divisions around the world isn’t necessarily new, but with a focus on social media powering named individuals at each company to keep their followers sitting on the edge of their seats means we get a lot more information. on how these companies operate. The downside to posting on social media is when certain images that expose unpublished information are not scrutinized by public relations or legal, and we can glimpse the next generation of technology. That’s what happened today.

Intel Customer Computing Group Executive Vice President and General Manager Gregory Bryant will be spending time at Intel’s R&D facility in Israel this week on his first Intel overseas trip in 2021. An early post on Sunday In the morning, showing Bryant’s trip to the gym to overcome jet lag, was followed by another later in the day with Bryant showing the offices and research. The post contained four photos, but it was quickly removed and replaced with a photo with three (in the tweet above). The deleted photo shows new information about next-generation Thunderbolt technology.

In this image we can see a poster on the wall showing ‘80G PHY technology‘, which means that Intel is working on a physical layer (PHY) for 80 Gbps connections. Right away, this is double the bandwidth of Thunderbolt 4, which runs at 40 Gbps.

The second line confirms that this is’USB 80G is designed to support the existing USB-C ecosystem‘, which follows that Intel aims to keep the USB-C connector but double the effective bandwidth.

The third line is actually where it gets technically interesting. ‘The PHY will be based on the novel PAM-3 modulation technology‘. It’s about how 0’s and 1’s are transmitted; traditionally we speak of NRZ encoding, which only allows transmitting a 0 or a 1, or a single bit. Natural progression is a scheme that allows two bits to be transferred, and this is called PAM-4 (Pulse Width Modulation), with 4 being the demarcation of how many different variants two bits can be seen (either as 00, 01, 10 , or 11). PAM-4, at the same frequency, has twice the bandwidth of an NRZ connection.

So what the heck in PAM-3?

Intel Executive Posts Thunderbolt 5 Photo then Deletes It 80
From Teledyne LaCroy on YouTube

PAM-3 is a technology in which the data line can carry a -1, a 0 or a +1. What the system does is combine two PAM-3 transmissions into a 3-bit data signal, as 000 is a -1 followed by a -1. This gets complex, so here is a table:

PAM-3 encoding
AnandTechTo transmit
1
To transmit
2
000-1-1
001-10
010-11
0110-1
10001
1011-1
11010
11111
Not used00

When we compare NRZ with PAM-3 and PAM-4, we can see that the data transfer rate for PAM-3 is in the middle of NRZ and PAM-4. The reason PAM-3 is being used in this case is to achieve that higher bandwidth without the additional limitations that PAM-4 requires to be enabled.

NRZ vs. PAM-3 vs. PAM4
AnandTechBitsCyclesBits per
Cycle
NRZ111
PAM-3321.5
PAM-4212

PAM-3 has similar limitations to NRZ.

1627847059 695 Intel Executive Posts Thunderbolt 5 Photo then Deletes It 80

The last line of this image is’[something] N6 test chip focusing on new PHY technology is working on [the lab and] showing promising results‘. That first word I thought was TSMC, but it has to be roughly the same width as the ‘The’ in the line above. So it doesn’t appear to be there, but N6 is a TSMC node.

Intel’s goal with Thunderbolt will be to boost bandwidth, power, and utility, but also at this point it seems that keeping it to the USB-C standard will be a vital part of keeping the technology useful for users who may fall back on connections. USB-C standard. Right now Intel’s TB4 is a superset that includes USB4, so we could see another situation where TB5 is also ready to be a superset of USB5, however, it seems that USB standards are slower to implement than TB standards at this time.

A special thanks to David Schor from WikiChip for the tip-off.

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