How Low Cost Can Chiplets Go? Depends on the Optimization, says AMD’s CEO Dr. Lisa Su

While not the first company on the market to talk about putting different types of silicon within the same package, AMD’s release of the Ryzen 3000 in July 2019 was the first to bring high-performance x86 computing via chiplets. The chiplet paradigm has worked very well for the company, with high-performance cores on optimized 7nm TSMC silicon, while cultivating the more analog operations on cheaper 14nm GlobalFoundries silicon and creating a high-speed interconnect between them. Compared to a monolithic design, AMD ends up using the best process for each feature, smaller chips that offer better performance and clustering, and the main cost aggregator becomes the packaging. But how low cost can these chiplet designs be? I posed this question to AMD’s CEO, Dr. Lisa Su.

In AMD’s consumer-focused product stack, the only products that ship with chipsets are the high-performance Ryzen 3000 and Ryzen 5000 series processors. These range in price from $199 for the six-core Ryzen 5 3600. , up to $799 for the 16-core Ryzen 9 5950X.

Everything else consumer-centric is a single piece of silicon, not chipsets. Everything in AMD’s mobile portfolio is based on single pieces of silicon, and they are also migrated to desktop form factors in AMD’s desktop APU strategy. We are seeing a clear delineation between where chiplets make financial sense and where they don’t. Of AMD’s latest generation of processors, the Ryzen 5 5600X still retails for $299.

One of the problems here is that a chiplet design requires additional packaging steps. The silicon that these processors are made from has to be on a PCB or substrate, and depending on what you want to do with the substrate can influence its cost. Chiplet designs require high-speed connections between chips, as well as power and communications with the rest of the system. The act of placing chiplets on a singular substrate is also cost effective, requiring precision, even if 99% accurate placement per chiplet on a substrate means a 3-chiplet product as a 3% loss in packaging yield, which increases costs. Beyond this, AMD first has to ship its 14nm dies for its products from New York to Asia, to be packaged with TSMC’s compute dies, before shipping the final product worldwide. That could be reduced in the future, as AMD is set to make its next-generation chipset designs in Asia.

Ultimately, there has to be a tipping point where simply building a monolithic silicon product is better for total cost than trying to ship chips and spending big bucks on new packaging techniques. I asked Dr. Lisa Su the question, acknowledging that AMD does not sell its latest generation for less than $300, as to whether $300 is the realistic turning point of the market from chiplet to non-chiplet.

Dr. Su explained how in their product design stages, AMD architects look at all possible ways to collect tiles. He explained that this means monolithic, chiplet, packaging, process technologies, as the number of potential variables in all of this have direct knock-on effects for the supply chain and cost and availability, as well as the final performance of the product. Dr. Su said to quote succinctly that AMD looks for what’s best for performance, power, cost, and what it says at tipping point may be true. That said, Dr. Su was keen not to say outright that this is the norm, detailing that she I would expect in the future that the dynamics will change as silicon costs increase, as this changes that optimization point. But it was clear from our discussions that AMD is always looking at the variables, with Dr. Su ending on a happy note that in the right time, you will see chiplets at the lower end of the market.

Personally, I think it’s quite telling that the market is very malleable for chiplets right now in the $300+ ecosystem. N7 (and N5) TSMC D0 yields are reportedly some of the best in the industry, meaning AMD mobile processors in the ~200mm square range can roll off the production line and serve everything up to that $300 value (and maybe a bit beyond). Going bigger brings die size performance constraints, where chiplets make sense. We are now at a stage where, if Moore’s law continues, how much computing capacity can fit on that 200mm2 silicon and which markets stand to benefit from it? Or will we get to a point where there will be a lot more features? They add that silicon sizes would increase, necessarily pushing everything down the chiplet path. As part of the discussion, Dr. Su mentioned scale economics when it comes to packaging, so it will be interesting to see how this dynamic plays out. But for now it looks like the way AMD will approach the sub-$300 market is going to be with next-gen hardware or monolithic silicon.

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